(1) Field of the Invention
This invention relates to integrated circuit semiconductor devices, and more particularly to a method for fabricating an array of memory cells for dynamic random access memory devices having tungsten (W) self-aligned capacitor node contacts to tungsten bit lines. The process integration also forms at the same time tungsten landing plug contacts in the peripheral circuits on the DRAM chip. This reduces the aspect ratio for the multilevel contacts and provides one-time formation of the landing plug contacts that minimizes substrate damage that would otherwise occur during multiple etching of the contact openings.
(2) Description of the Prior Art
The number and density of memory cells on the DRAM chip has dramatically increased in recent years. By the year 2000 the number of memory cells on a chip is expected to reach 1 Gigabit. This increase in circuit density has resulted from the downsizing of the individual semiconductor devices (FETs) and the resulting increase in device packing density. The reduction in device size is due in part to advances in high resolution photolithography and directional (anisotropic) plasma etching. In the non-self-aligned process of the prior art, the contact openings for the bit lines are made first, and the bit lines are formed. The openings for the capacitor node contacts are then made and alignment tolerances are required between the bit lines and the node contacts that limit the cell density. That is, without self-alignment techniques, the cell size must be increased in order to allow for the misalignment error between the node contacts and the bit lines. Therefore, it is desirable to have self-aligned bit lines to the capacitor node contacts.
One method for forming self-aligned bit-line-to-capacitor-node contacts is described by Park et al., U.S. Pat. No. 5,332,685, in which bit-line contact openings and node contact openings are etched at the same time. A polysilicon or metal layer is deposited and etched back to fill the openings. After forming the bit lines that are insulated, the capacitor bottom electrodes are formed self-aligned to the bit lines. Another method of forming high-density DRAM circuits is described by Jeng et al., U.S. Pat. N0. 5,510,073, in which the bit-line contacts and the capacitor node contacts are simultaneously etched. A conducting layer having a cap oxide is then patterned to form the bit lines and bit-line contacts, while leaving portions of the conducting layer in the capacitor node contacts. The capacitor bottom electrodes are then formed self-aligned to the bit lines. Another method for making DRAM circuits is described Arimoto, U.S. Pat. No. 5,045,899, with the objective of reducing capacitance between the bit lines and the capacitors, and to reduce inter-bit-line capacitance.
Several methods of making tungsten/titanium nitride (W/TiN) contacts to substrates are also described in the literature. One method of forming W/TiN contacts is described by Pintchovski et al., U.S. Pat. No. 4,822,753, in which a Ti/TiN barrier layer is formed prior to depositing the CVD W layer using tungsten hexafluoride to prevent erosion of the silicon substrate. And another method of making W/TiN contacts is described by Somekh et al., U.S. Pat. No. 5,250,467, which provides a Ti/TiN layer to improve the adhesion when the W plug is formed in a contact opening in an insulator on the silicon substrate.
Another problem associated with fabricating DRAM circuits but not addressed in the prior art, is the need to form reliable contacts or via holes for the multilevel of electrical interconnections. The multilevel metal inter-connect structure must be planar to provide a distortion-free photoresist mask that would otherwise result from a shallow Depth Of Focus (DOF) during optical exposure. The planar surface is also required to reliably pattern the conducting layer by directional (plasma) etching without leaving metal residue that can cause intralevel electrical shorts. However, the reduction in critical dimensions (CD) and planar surface result in the need to etch high-aspect-ratio contact openings (or via holes) of varying depths in the interlevel dielectric (ILD) layers, which is not addressed in the current technology.
Therefore there is still a need in the industry to provide a process that forms both self-aligned node contacts to bit lines for DRAM devices while reducing the high aspect ratio of the contact or via holes in the ILD.